Synopsys Announces New Test Technology Addressing Capacity, Complexity and Quality Challenges in Today's SOC Design Flows

BALTIMORE--(BUSINESS WIRE)--Oct. 29, 2001--INTERNATIONAL TEST CONFERENCE--

New Capability in DFT Compiler Improves Capacity and

Performance by More Than 300 Percent, and TetraMAX DelayTest

Targets Strict New Test Requirements

Synopsys, Inc. (Nasdaq:SNPS - news) advances its leadership position in device test today with the introduction of new technology and capabilities in the company's design-for-test (DFT) and automatic test pattern generation (ATPG) products. The ability for designers to successfully implement test for multimillion gate, system on chip (SoC) devices is strengthened by new capabilities in Synopsys' DFT Compiler. These new capabilities leverage advanced test modeling technology for dramatic capacity and performance gains in the tool. In addition, Synopsys' new TetraMAX® ATPG delay test option now provides comprehensive capabilities to help designers detect timing-related defects during manufacturing test, in order to meet strict corporate quality mandates.

High Capacity/Performance Flow

With the size and complexity of today's advanced ASICs and SoCs, designers' ability to efficiently implement test in these devices is a critical productivity challenge. DFT Compiler's new test modeling technology now supports advanced hierarchical DFT flows in Synopsys' physical synthesis environment. The new modeling technology increases the tool's capacity by more than 3X, while increasing its speed by 7X with no impact on the product's ability to implement timing- and layout-optimized DFT. This improvement in the capacity and performance of the industry's most widely adopted test synthesis tool will help designers keep pace with design growth and complexity.

"With our design size and complexity increasing exponentially, we needed a hierarchical scan synthesis solution that will help reduce not only the overall design cycle time, but also be easy to use and transparent to the designers," said Mike Fazeli, worldwide director of electronic design automation for DSP-based Designs at Texas Instruments. "The new, advanced hierarchical scan synthesis flow capability in DFT Compiler meets our design complexity requirements and we believe that the new features in DFT Compiler will help us achieve additional productivity across a wide spectrum of designs."

Transition and Path Delay Fault ATPG with TetraMAX DelayTest

Up to half of manufacturing defects in today's designs are timing related and may not be caught without specifically targeting delay defects. TetraMAX DelayTest offers a structured, scan-based approach to delay testing, predictable and measurable delay test coverage, and ensures compatibility with low-cost automatic test equipment. TetraMAX DelayTest lets designers easily create test patterns to target the most common timing-related defect models--transition delay faults and path delay faults. Moreover, TetraMAX DelayTest integration with Synopsys' PrimeTime®, the industry's leading static timing analysis tool, further enhances the tool flow and interoperability.

Benoit Bailliet, DFT leader for Motorola's 3G Baseband Products, commented, "We were very pleased with our first results from TetraMAX DelayTest. In a matter of hours, we were able to extract a list of critical paths at the module level using PrimeTime, map those paths to the SoC level, and generate path delay patterns with TetraMAX ATPG. These patterns successfully ran on silicon that same day. This was a real achievement for our path delay testing methodology on this 100 million transistor design."

"Achieving fully testable semiconductor devices today requires that DFT products stay ahead of the design complexity curve," said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test Business Unit. "We have extended our award-winning TetraMAX tool to keep pace with increasing ATPG requirements. In addition, we have made breakthroughs with the effective use of advanced test modeling technology in DFT Compiler that we believe will become a foundation of DFT for complex multi-million gate SoCs. This new test modeling technology is based on the proposed IEEE P1450.6 Core Test Language (CTL) standard, underscoring Synopsys' commitment to build DFT tools on open standards, while continuing to deliver unique capabilities that enable our customers to achieve DFT closure."

Pricing and Availability

The new capability in DFT Compiler begins shipping in December 2001. Current DFT Compiler customers will receive this capability at no additional charge as a maintenance update. Pricing for DFT Compiler begins at $22,500 US list for a one-year technology subscription license (TSL). The DelayTest option to TetraMAX ATPG is currently available. Pricing begins at $36,660 US list for a one-year TSL.

Synopsys' Versatile Test Solutions

Synopsys, the leading supplier of IC test automation solutions, offers a complete line of integrated products and services to meet the most demanding manufacturing test requirements. The company's award-winning design-for-test offering includes the advanced DFT Compiler and TetraMAX ATPG tools. DFT Compiler incorporates the latest generation of Synopsys' patented 1-Pass test synthesis technology and enables design teams to efficiently meet their DFT closure goals. TetraMAX complements scan-based test methodologies by providing industry leading ATPG performance, capacity and ease of use. Complementing these products, Synopsys offers comprehensive test services delivered by a world-class team of DFT experts.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS - news), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Synopsys, TetraMAX and PrimeTime are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

     Synopsys, Inc.
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